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lt3782 1 3782fg typical application features applications description 2-phase step-up dc/dc controller the lt ? 3782 is a current mode two phase step-up dc/dc converter controller. its high switching frequency (up to 500khz) and 2-phase operation reduce system ? ltering capacitance and inductance requirements. with 10v gate drive (v cc 13v) and 4a peak drive current, the lt3782 can drive most industrial grade high power mosfets with high ef? ciency. for synchronous applica- tions, the lt3782 provides synchronous gate signals with programmable falling edge delay to avoid cross conduc- tion when using external mosfet drivers. other features include programmable undervoltage lockout, soft-start, current limit, duty cycle clamp (50% or higher) and slope compensation. the lt3782 is available in thermally enhanced 28-lead tssop and 4mm 5mm qfn packages. for new designs use the lt3782a which has improved phase matching l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6144194. n industrial equipment n telecom infrastructure n interleaved isolated power supply n 2-phase operation reduces required input and output capacitance n programmable switching frequency: 150khz to 500khz n 6v to 40v input range n 10v gate drive with v cc 13v n high current gate drive (4a) n programmable soft-start and current limit n programmable slope compensation for high noise immunity n mosfet gate signals with programmable falling edge delay for external synchronous drivers n programmable undervoltage lockout n programmable duty cycle clamp (50% or higher) n thermally enhanced 28-lead tssop and 4mm 5mm qfn packages 50v 4a boost converter 3782 ta01 6.8nf 13k 0.1f 10nf c in 10f 50v 2x r freq 80k r slope 59k r s1 0.004 m1si7852dp 2x 1f r8 274k r6 825k c out2 220f v out 50v, 4a v in 10v to 36v + c32f + r s2 0.004 lt3782 v cc runslope delay dcl r set ssv c gbias2 gbias bgate1 v ee1 bgate2 v ee2 sense1 + sense1 C sense2 + sense2 C fb gnd m2si7852dp 2x gbias1 10 10nf 10 r f1 475k l1 d1 30bq060 d2 30bq060 l2 100pf r f2 24.9k c out1 10f50v 2x l1, l2: pb2020.223c in , c out1 : x7r, tdk ef? ciency and power loss vs load current i out (a) 0 efficiency (%) 4 3782 ta01b power loss (w) 1815 12 9 6 3 0 1 2 3 5 v in = 12v v in = 12v v in = 24v v in = 24v efficiency power loss 9793 9591 89 87 85 not recommended for new designs contact linear technology for potential replacement downloaded from: http:///
lt3782 2 3782fg t jmax = 125c, ja = 38c/ w exposed pad (pin 29) is gnd, must be soldered to pcb v cc supply voltage ...................................................40v gbias, gbias1, gbias2 pin (externally forced) ....................................................14v sync, run pin .........................................................30v operating junction temperature range (notes 2, 3) ................................. C40c to 125c (note 1) storage temperature range ...................C 65c to 150c lead temperature (soldering, 10 sec) .................. 300c ss ................................................................ C0.3v to 6v sense1 + , sense2 + , sense1 C , sense2 C ..................................... C0.3v to 2v 12 3 4 5 6 7 8 9 1011 12 13 14 top view fe package 28-lead plastic tssop 2827 26 25 24 23 22 21 20 19 18 17 16 15 sgate2 sgate1 nc gnd sync delay dcl sense1 + sense1 C slope r set sense2 C sense2 + ss gbiasv cc ncnc v ee1 bgate1 gbias1 gbias2 bgate2 v ee2 ncrun fb v c 29 9 10 top view 29 ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 sync delay dcl sense1 + sense1 C slope r set sense2 C bgate1 gbias1 nc nc gbias2 bgate2 v ee2 nc gnd sgate1 sgate2 gbias v cc v ee1 nc sense2 + ss v c fb run 7 17 18 19 20 21 2216 8 15 t jmax = 125c, ja = 37c/ w exposed pad (pin 29) is gnd, must be soldered to pcb absolute maximum ratings pin configuration order information lead free finish tape and reel part marking package description temperature range lt3782efe#pbf lt3782efe#trpbf lt3782efe 28-lead plastic tssop C40c to 85c lt3782ife#pbf lt3782ife#trpbf lt3782ife 28-lead plastic tssop C40c to 125c lt3782eufd#pbf lt3782eufd#trpbf 3782 28-lead (4mm 5mm) plastic qfn C40c to 85c lead based finish tape and reel part marking package description temperature range lt3782efe lt3782efe#tr lt3782efe 28-lead plastic ssop C40c to 85c lt3782ife lt3782ife#tr lt3782ife 28-lead plastic ssop C40c to 125c lt3782eufd lt3782eufd#tr 3782 28-lead (4mm 5mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
lt3782 3 3782fg the denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c. v cc = 13v, r set = 80k, no load on any outputs, unless otherwise noted. parameter conditions min typ max units overall supply voltage (v cc ) l 64 0 v supply current (i vcc )v c 0.5v (switching off), v cc 40v 11 16 ma shutdownrun threshold l 2.3 2.45 2.6 v run threshold hysteresis 80 mv supply current in shutdown 1v run v ref , v cc 30v run 0.3v, v cc 30v 0.4 40 0.65 90 ma a run pin input current v run = 2.3v l C0.5 C2 a voltage ampli? er g m reference voltage (v ref ) l 2.42 2.4 2.44 2.464 2.488 vv transconductance v vc = 1v, i vc = 2a l 200 260 370 mho input current i fb v fb = v ref l 0.2 0.6 a v c high i vc = 0 1.5 v v c low i vc = 0 0.35 0.4 v source current i vc v vc = 0.7v C 1v, v fb = v ref C 100mv 8 11 14 a sink current i vc v vc = 0.7v C 1v, v fb = v ref + 100mv 13 20 28 a v c threshold for switching off (bgate1, bgate2 low) l 0.3 v soft-start current i ss v ss = 0.1v C 2.8v 6 10 15 a current ampli? er ca1, ca2 voltage gain v c /v sense 4 current limit (v sense1 + C v sense1 C ) (v sense2 + C v sense2 C ) 5 06 28 0 m v input current (i sense1 + , i sense1 C , i sense2 + , i sense2 C ) v sense = 0v 60 a oscillatorswitching frequency r set = 130k r set = 80k r set = 40k ll l 130212 386 154250 465 177288 533 khzkhz khz synchronization pulse threshold on sync pin rising edge v sync 0.8 1.2 2 v synchronization frequency range(note: operation switching frequency equals half of the synchronization frequency) r set = 130k r set = 80k r set = 40k 180290 550 240392 715 khzkhz khz v rset r set = 80k 2.3 v maximum duty cycle v fb = v ref C 25mv, r set > 80k r set = 40k ll 9083 9490 %% duty cycle limit r set = 80k, v dcl 0.3v v dcl = 1.2v v dcl = v rset 5075 max duty cycle %% dcl pin input current v dcl 0.3v l C0.1 C0.3 a electrical characteristics downloaded from: http:///
lt3782 4 3782fg the denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c. v cc = 13v, r set = 80k, no load on any outputs, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3782e is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3782i is guaranteed to meet performance speci? cations over the full C40c to 125c operating junction temperature range. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. electrical characteristics parameter conditions min typ max units gate driverv gbias i gbias < 70ma l 10.2 11 11.7 v bgate1, bgate2 high voltage 13v v cc 24v, i bgate = C100ma v cc = 8v, i bgate = C100ma ll 7.83.8 9.2 5 10.5 v v bgate1, bgate2 source current (peak) capacitive load >22f capacitive load >50f 34 aa bgate1, bgate2 low voltage 8v v cc 24v, i bgate = 100ma l 0.5 0.7 v bgate1, bgate2 sink current (peak) capacitive load >22f capacitive load >50f 34 aa sgate1, sgate2 high voltage 8v v cc 24v, i sgate = C20ma l 4.5 5.5 6.7 v sgate1, sgate2 low voltage 8v v cc 24v, i sgate = 20ma 0.5 0.7 v sgate1, sgate2 peak current 500pf load 100 ma delay of bgate high delay pin and r set pin shorted v delay = 1v v delay = 0.5v v delay = 0.25v 100150 250 500 nsns ns ns delay pin input current v delay = 0.25v l C0.1 C0.3 a downloaded from: http:///
lt3782 5 3782fg junction temperature (c) 0 reference voltage (v) 2.4462.444 2.442 2.440 2.438 2.436 2.434 50 100 125 75 3782 g05 25 150 v cc (v) 6 i cc (ma) 2018 16 12 1410 86 4 2 0 22 3782 g02 10 8 121620 26 14 18 30 24 28 v cc (v) 6 v ref (mv) 30 3782 g03 12 18 24 27 9 15 21 32 1 0 C1C2 C3 C4 C5 frequency (khz) 1210 8 6 42 0 C2 C4 frequency v ref r freq (k) 0 frequency (khz) 600500 400 300 200 100 160 3782 g04 40 20 60 100 140 80 120 200 180 time (s) 0 v gbias (v) 1410 62 12 84 0 C2 i gbias (ma) 800600 400 200 700500 300 100 0 750 3782 g06 250 500 1m v gbias i gbias v delay (v) 0 delay (ns) 1000 900800 600 700500 400 300 200 100 0 2.0 3782 g07 0.5 1.0 1.5 2.5 switching frequency (khz) 100 duty cycle (%) 105100 9590 85 80 500 3782 g08 200 300 400 600 v dcl (v) 0 maximum duty cycle (%) 2.4 3782 g09 0.6 1.2 1.8 2.1 0.3 0.9 1.5 120110 100 9080 70 60 50 40 i gbias (ma) 0 v gbias (v) 10.5 100 3782 g01 10.0 10.6 10.1 10.7 10.2 10.8 10.3 10.9 10.4 50 11.0 v gbias vs i gbias i cc vs v cc ?v ref vs v cc , ?frequency vs v cc (r set = 80k) switching frequency vs r freq reference voltage vs temperature v gbias vs i gbias at start-up (charging 2f) sgate (low) to bgate (high) delay vs v delay (r set = 80k) switching frequency vs duty cycle maximum duty cycle limit vs v dcl (r set = 80k) t a = 25c unless otherwise noted. typical performance characteristics downloaded from: http:///
lt3782 6 3782fg sgate2 (pin 1/pin 26): second phase synchronous drive signal. an external driver buffer is needed to drive the top synchronous power fet. sgate1 (pin 2/pin 27): first phase synchronous drive signal. an external driver buffer is needed to drive the top synchronous power fet. gnd (pin 4/pin 28): chip ground. sync (pin 5/pin 1): synchronization input. the pulse width can range from 10% to 70%. note that the operating frequency is half of the sync frequency. delay (pin 6/pin 2): when synchronous drivers are used, the programmable delay that delays bgate turns on after sgate turns off. dcl (pin 7/pin 3): this pin programs the limit of the maxi- mum duty cycle. when connected to v rset , it operates at natural maximum duty cycle, approximately 90%.sense1 + (pin 8/pin 4): first phase current sense ampli? er positive input. an rc ? lter is required across the current sense resistor. current limit threshold is set at 60mv. sense1 C (pin 9/pin 5): first phase current sense ampli? er negative input. an rc ? lter is required across the current sense resistor. slope (pin 10/pin 6): a resistor from slope to gnd increases the internal current mode pwm slope com- pensation. r set (pin 11/pin 7): a resistor from r set to gnd sets the oscillator charging current and the operating frequency. sense2 C (pin 12/pin 8): second phase current sense ampli? er negative input. an rc ? lter is required across the current sense resistor. sense2 + (pin 13/pin 10): second phase current sense ampli? er positive input. an rc ? lter is required across the current sense resistor. current limit threshold is set at 60mv. ss (pin 14/pin 11): soft-start. a capacitor on this pin sets the output ramp up rate. the typical time for ss to reach the programmed level is (c ? 2.44v)/10a. v c (pin 15/pin 12): the output of the g m error ampli? er and the control signal of the current loop of the current-mode pwm. switching starts at 0.7v, and higher v c voltages corresponds to higher inductor current.fb (pin 16/pin 13): error ampli? er inverting input. a resistor divider to this pin sets the output voltage.run (pin 17/pin 14): lt3782 goes into shutdown mode when v run is below 2.2v and goes to low bias current shutdown mode when v run is below 0.3v. v ee2 (pin 19/pin 16): gate driver bgate2 ground. this pin should be connected to the ground side of the second current sense resistor. bgate2 (pin 20/pin 17): second phase mosfet driver. gbias2 (pin 21/pin 18): bias for gate driver bgate2. should be connected to gbias or an external power supply between 12v to 14v. a bypass low esr capacitor of 2f or larger is needed and should be connected directly to the pin to minimize parasitic impedance. gbias1 (pin 22/pin 21): bias for gate driver bgate1. should be connected to gbias2. bgate1 (pin 23/pin 22): first phase mosfet driver. v ee1 (pin 24/pin 23): gate driver bgate1 ground. this pin should be connected to the ground side of the second current sense resistor. v cc (pin 27/pin 24): chip power supply. good supply bypassing is required.gbias (pin 28/pin 25): internal 11v regulator output for biasing internal circuitry. should be connected to gbias1 and gbias2. exposed pad (pin 29/pin 29): the exposed package pad is fused to internal ground and is for heat sinking. solder the bottom metal plate onto expanded ground plane for optimum thermal performance. nc (pins 3, 18, 25, 26/pins 9, 15, 19, 20): not connected. can be connected to gnd. (fe/ufd) pin functions downloaded from: http:///
lt3782 7 3782fg gbias2 r250k a18 one shot a19 a2 60mv ch1 cl1 pwm1 a3 r3 3782 bd c22nf c in 20f r freq r s1 m1 r8 r6 c out 100f v out v in + c32f r s2 v cc run sync delay delay delay slope r set dcl r set gnd c12000pf r52k c710nf gbias2gbias gbias1 bgate1 bgate1 bgate1 sgate1 bgate2 v ee1 v ee2 v ref sense1 + sense1 C sense2 + sense2 C fb m2 gbias1 r710 c42nf r910 r f2 r f1 r150k l1 15 d1 d2 l2 15 C + C + 6 5 17 27 10 7 v c 15 ss 14 11 4 sgate1 sgate2 1 2 22 21 28 23 8 9 24 20 13 12 19 16 regulator slope comp osc logic q ck q d ch1 set rs 7v + C + 0.5v + C + 2.44v + C + 2.5v + v cc C 2.5v a6 a11 a12 a5 a7 a8 low powershutdown v gbias = v cc C 1v and clamped at 11v note: package bottom metal plate (pin 29) is fused to chip die agnd a20 a1 a4 a17 a15 a13 c5 20pf + one shot blanking a14 a9 C + C + slope comp 60mv a10 r4 blanking C + + C C + ch2 rs slope comp 4v bgate2 C + 2.5v + + + gm d6 d7 d4 i1 10a ch2 cl2 pwm2 a16 set block diagram downloaded from: http:///
lt3782 8 3782fg operation the lt3782 is a two phase constant frequency current mode boost controller. switching frequency can be programmed up to 500khz. during normal switching cycles, the two channels are controlled by internal ? ip-? ops and are 180 degrees out-of-phase. referring to the block diagram, the lt3782s basic func- tions include a transconductance amplifer (g m ) to regulate the output voltage and to control the current mode pwm current loop. it also includes the necessary logic and ? ip- ? op to control the pwm switching cycles, two high speed gate drivers to drive high power n-channel mosfets, and 2-phase control signals to drive external gate drivers for optional synchronous operation. in normal operation, each switching cycle starts with a switch turn-on. the inductor current of each channel is sampled through the current sense resistor and ampli? ed then compared to the error ampli? er output v c to turn the switch off. the phase delay of the second channel is controlled by the divide-by-two d ? ip-? op and is exactly 180 degrees out-of-phase of the ? rst channel. with a re- sistor divider connected to the fb pin, the output voltage is programmed to the desired value. the 10v gate drivers are suf? cient to drive most high power n-channel mosfet in many industrial applications. additional important features include shutdown, cur- rent limit, soft-start, synchronization and programmable maximum duty cycle. additional slope compensation can be added also. output voltage programming with a 2.44v feedback reference voltage v ref , the output v out is programmed by a resistor divider as shown in the block diagram. v out = 2.44 1 + r f1 r f 2 soft-start and shutdownduring soft-start, the voltage on the ss pin (v ss ) controls the output voltage. the output voltage thus ramps up fol-lowing v ss . the effective range of v ss is from 0v to 2.44v. the typical time for the output to reach the programmed level is t = c ? 2.44v 10 a c is the capacitor connected from the ss pin to gnd. undervoltage lockout and shutdown only when v run is higher than 2.45v v gbias will be ac- tive and the switching enabled. the lt3782 goes into low current shutdown when v run is below 0.3v. a resistor divider can be used on run pin to set the desired v cc undervoltage lockout voltage. 80mv of hysteresis is built in on run pin thresholds. oscillation frequency setting and synchronization the switching frequency of lt3782 can be set up to 500khz by a resistor r freq from pin r set to ground. for f set = 250khz, r freq = 80k once the switching frequency f set is chosen, r freq can be found from the switching frequency vs r freq graph found under the typical performance characteristics section. note that because of the 2-phase operation, the internal oscillator is running at twice the switching frequency. to synchronize the lt3782 to the system frequency f system , the synchronizing frequency f sync should be two times f system , and the lt3782 switching frequency f set should be set below 80% of f system . f sync = 2f system and f set < (f system ? 0.8) for example, to synchronize the lt3782 to 200khz system frequency f system , f sync needs to be set at 400khz and f set needs to be set at 160khz. from the switching frequency vs r freq graph found under the typical performance characteristics section, r freq = 130k. applications information downloaded from: http:///
lt3782 9 3782fg with a 200ns one-shot timer on chip, the lt3782 provides ? exibility on the external sync pulse width. the sync pulse threshold is about 1.2v (figure 1). current limit current limit is set by the 60mv threshold across sen1p , sen1n for channel one and sen2p, sen2n for channel two. by connecting an external resistor r s (see block diagram), the current limit is set for 60mv/r s . r s should be placed very close to the power switch with very short traces. a low pass r c ? lter is needed across r s to ? lter out the switching spikes. good kelvin sensing is required for accurate current limit. the input bypass capacitor ground should be at the same ground point of the current sense resistor to minimize the ground current path. synchronous recti? er switches for high output voltage applications, the power loss of the catch diodes are relatively small because of high duty cycle. if diodes power loss or heat is a concern, the lt3782 provides pwm signals through sgate1 and sgate2 pins to drive external mosfet drivers for synchronous recti- ? er operation. note that sgate drives the top switch and bgate drives the bottom switch. to avoid cross conduction between top and bottom switches, the bgate turn-on is delayed 100ns (when delay pin is tied to r set pin) from sgate turn-off (see figure 2). if a longer delay is needed to compensate for the propagation delay of external gate driver, a resistor divider can be used from r set to ground to program v delay for the longer delay needed. for example, for a switching frequency of 250khz and delay of 150ns, figure 1. synchronizing with external clock figure 2. delay timing 5v to 20v vn2222 pulse width > 200ns 5k sync 3782 f01 lt3782 3782 f02 delay bgate1 sgate1 set applications information downloaded from: http:///
lt3782 10 3782fg then r freq1 + r freq2 should be 80k and v delay should be 1v, with v rset = 2.3v then r freq1 = 47.5k and r freq2 = 32.5k (see figure 3).duty cycle limit when dcl pin is shorted to r set pin and switching fre- quency is less than 250khz (r freq > 80k), the maximum duty cycle of lt3782 will be at least 90%. the maximum duty cycle can be clamped to 50% by grounding the dcl pin or to 75% by forcing the v dcl voltage to 1.2v with a resistor divider from r set pin to ground. the typical dcl pin input current is 0.2a.slope compensation the lt3782 is designed for high voltage and/or high current applications, and very often these applications generate noise spikes that can be picked up by the cur- rent sensing ampli? er and cause switching jitter. to avoid switching jitter, careful layout is absolutely necessary to minimize the current sensing noise pickup. sometimes increasing slope compensation to overcome the noise can help to reduce jitter. the built-in slope compensa- tion can be increased by adding a resistor r slope from slope pin to ground. note that smaller r slope increases slope compensation and the minimum r slope allowed is r freq /2. layout considerations to prevent emi, the power mosfets and input bypass capacitor leads should be kept as short as possible. a ground plane should be used under the switching circuitry to prevent interplane coupling and to act as a thermal spreading path. note that the bottom pad of the package is the heat sink, as well as the ic signal ground, and must be soldered to the ground plane. in a boost converter, the conversion gain (assuming 100% ef? ciency) is calculated as (ignoring the forward voltage drop of the boost diode): v out v in = 1 1 d where d is the duty ratio of the main switch. d can then be estimated from the input and output voltages: d = 1 v in v out ;d max = 1 v in(min) v out figure 3. increase delay time r set delay lt3782 r freq2 32.5k r freq1 47.5k 3782 f03 applications information downloaded from: http:///
lt3782 11 3782fg the peak and average input currents the control circuit in the lt3782 measures the input current by using a sense resistor in each mosfet source, so the output current needs to be re? ected back to the input in order to dimension the power mosfet properly. based on the fact that, ideally, the output power is equal to the input power, the maximum average input current is: i in(max) = i o(max ) 1? d max the peak current is: i in(peak) = 1.2 ? i o(max ) 1? d max the maximum duty cycle, d max , should be calculated at minimum v in . power inductor selection in a boost circuit, a power inductor should be designed to carry the maximum input dc current. the inductance should be small enough to generate enough ripple current to provide adequate signal to noise ratio to the lt3782. an empirical starting of the inductor ripple current (per phase) is about 40% of maximum dc current, which is half of the input dc current in a 2-phase circuit: i l ? 40% ? i out(max) ?v out 2v in = 20% ? i out(max) ?v out v in where v in , v out and i out are the dc input voltage, output voltage and output current, respectively. and the inductance is estimated to be: l = v in ?d f s ? i l where f s is the switching frequency per phase. the saturation current level of inductor is estimated to be: i sat i l 2 + i in 2 ? 70% ? i out(max) ?v out v in(min) sense resistor selection during the switch on-time, the control circuit limits the maximum voltage drop across the sense resistor to about 60mv. the peak inductor current is therefore limited to 60mv/r. the relationship between the maximum load current, duty cycle and the sense resistor r sense is: r v sense(max) ? 1? d max 1.2 ? i o(max ) 2 power mosfet selectionimportant parameters for the power mosfet include the drain-to-source breakdown voltage (bv dss ), the threshold voltage (v gs(th) ), the on-resistance (r ds(on) ) versus gate- to-source voltage, the gate-to-source and gate-to-drain charges (q gs and q gd , respectively), the maximum drain current (i d(max) ) and the mosfets thermal resistances (r th(jc) and r th(ja) ). applications information downloaded from: http:///
lt3782 12 3782fg the gate drive voltage is set by the 10v gbias regulator. consequently, 10v rated mosfets are required in most high voltage lt3782 applications. pay close attention to the bv dss speci? cations for the mosfets relative to the maximum actual switch voltage in the application. the switch node can ring during the turn-off of the mosfet due to layout parasitics. check the switching waveforms of the mosfet directly across the drain and source terminals using the actual pc board layout (not just on a lab breadboard!) for excessive ringing. calculating power mosfet switching and conduction losses and junction temperatures in order to calculate the junction temperature of the power mosfet, the power dissipated by the device must be known. this power dissipation is a function of the duty cycle, the load current and the junction temperature itself (due to the positive temperature coef? cient of its r ds(on) ). as a result, some iterative calculation is normally required to determine a reasonably accurate value. care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (line voltage and temperature), and for the worst-case speci- ? cations for v sense(max) and the r ds(on) of the mosfet listed in the manufacturers data sheet. the power dissipated by the mosfet in a 2-phase boost converter is: p fet = i o(max) 2 1? d ( ) 2 ?r ds(on) ?d? t + k?v o 2 ? i o(max) 2 1? d ( ) ?c rss ?f the ? rst term in the equation above represents the i 2 r losses in the device, and the second term, the switching losses. the constant, k = 1.7, is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. the t term accounts for the temperature coef? cient of the r ds(on) of the mosfet, which is typically 0.4%/c. figure 4 illustrates the variation of normalized r ds(on) over temperature for a typical power mosfet. junction temperature (c) C50 t normalized on resistance 1.0 1.5 150 3782 f06 0.5 0 0 50 100 2.0 figure 4. normalized r ds(on) vs temperature applications information downloaded from: http:///
lt3782 13 3782fg from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following formula: t j = t a + p fet ? r th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the case to the ambient temperature (r th(ca) ). this value of t j can then be compared to the original, assumed value used in the iterative calculation process.input capacitor choice the input capacitor must have high enough voltage and ripple current ratings to handle the maximum input voltage and rms ripple current rating. the input ripple current in a boost circuit is very small because the input current is continuous. with 2-phase operation, the ripple cancellation will further reduce the input capacitor ripple current rating. the ripple current is plotted in figure 5. please note that the ripple current is normalized against i norm = v in l?f s output capacitor selectionthe voltage rating of the output capacitor must be greater than the maximum output voltage with suf? cient derat- ing. because the ripple current in output capacitor is a pulsating square wave in a boost circuit, it is important that the ripple current rating of the output capacitor be high enough to deal with this large ripple current. figure 6 shows the output ripple current in the 1- and 2-phase designs. as we can see, the output ripple current of a 2-phase boost circuit reaches almost zero when the duty cycle equals 50% or the output voltage is twice as much as the input voltage. thus the 2-phase technique signi? cantly reduces the output capacitor size. figure 6. normalized output rms ripple currents in boost converter: 1-phase and 2-phase. i out is the dc output current. 0.1 i oripple /i out 0.9 3782 f05 0.3 0.5 0.7 0.8 0.2 0.4 0.6 3.253.00 2.75 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 duty cycle or (1-v in /v out ) 1-phase 2-phase figure 5. normalized input peak-to-peak ripple current duty cycle 0 i in /i norm 1.000.90 0.80 0.60 0.700.50 0.40 0.30 0.20 0.10 0 0.8 3782 f04 0.2 0.4 0.6 1.0 1-phase 2-phase applications information i norm = v in l?f s the rms ripple current is about 29% of the peak-to-peak ripple current. downloaded from: http:///
lt3782 14 3782fg for a given v in and v out , we can calculate the duty cycle d and then derive the output rms ripple current from figure 6. after choosing output capacitors with suf? cient rms ripple current rating, we also need to consider the esr requirement if electrolytic caps, tantulum caps, poscaps or sp caps are selected. given the required output ripple voltage spec v out (in rms value) and the calculated rms ripple current i out , one can estimate the esr value of the output capacitor to be esr v out i out external regulator to bias gate driversfor applications with v in higher than 24v, the ic temperature may get too high. to reduce heat, an external regulator between 12v to 14v should be used to override the internal v gbias regulator to supply the current needed for bgate1 and bgate2 (see figure 7). ef? ciency considerations the ef? ciency of a switching regulator is equal to the out- put power divided by the input power (100%). percent ef? ciency can be expressed as: % ef? ciency = 100% C (l1 + l2 + l3 + ), where l1, l2, etc. are the individual loss components as a percentage of the input power. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources usually ac- count for the majority of the losses in lt3782 application circuits: 1. the supply current into v in . the v in current is the sum of the dc supply current i q (given in the electrical char- acteristics) and the mosfet driver and control currents. the dc supply current into the v in pin is typically about 7ma and represents a small power loss (much less than 1%) that increases with v in . the driver current results from switching the gate capacitance of the power mosfet; this current is typically much larger than the dc current. each time the mosfet is switched on and then off, a packet of gate charge q g is transferred from gbias to ground. the resulting dq/dt is a current that must be supplied to the gbias capacitor through the v in pin by an external supply. in normal operation: i q(tot) i q = f ? q g p ic = v in ? (i q + f ? q g ) figure 7 3782 f07 2f 12v + gbias gbias1gbias2 lt3782 applications information downloaded from: http:///
lt3782 15 3782fg 2. power mosfet switching and conduction losses: p fet = i o(max) 2 1? d ma x 2 ?r ds(on) ?d max ? t + k?v o 2 ? i o(max) 2 1? d ma x ?c rss ?f 3. the i 2 r losses in the sense resistor can be calculated almost by inspection. p r(sense) = i o(max) 2 1? d ma x 2 ?r?d max 4. the losses in the inductor are simply the dc input cur- rent squared times the winding resistance. expressing this loss as a function of the output current yields: p r(winding) = i o(max) 2 1? d ma x 2 ?r w 5. losses in the boost diode. the power dissipation in the boost diode is: p diode = i o(max ) 2 ?v d the boost diode can be a major source of power loss in a boost converter. for 13.2v input, 42v output at 3a, a schottky diode with a 0.4v forward voltage would dissipate 600mw, which represents about 1% of the input power. diode losses can become signi? cant at low output voltages where the forward voltage is a signi? cant percentage of the output voltage. 6. other losses, including c in and c o esr dissipation and inductor core losses, generally account for less than 2% of the total losses. pcb layout considerations to achieve best performance from an lt3782 circuit, the pc board layout must be carefully done. for lower power applications, a two-layer pc board is suf? cient. however, at higher power levels, a multiplayer pc board is recom- mended. using a solid ground plane under the circuit is the easiest way to ensure that switching noise does not affect the operation. in order to help dissipate the power from mosfets and diodes, keep the ground plane on the layers closest to the layers where power components are mounted. use power planes for mosfets and diodes in order to improve the spreading of the heat from these components into the pcb. applications information downloaded from: http:///
lt3782 16 3782fg for best electrical performance, the lt3782 circuit should be laid out as follows: place all power components in a tight area. this will minimize the size of high current loops. orient the input and output capacitors and current sense resistors in a way that minimizes the distance between the pads connected to ground plane. place the lt3782 and associated components tightly to- gether and next to the section with power components. use a local via to ground plane for all pads that connect to ground. use multiple vias for power components. connect the current sense inputs of lt3782 directly to the current sense resistor pads. connect the current sense traces on the opposite sides of pads from the traces carrying the mosfets source currents to ground. this technique is referred to as kelvin sensing. applications information downloaded from: http:///
lt3782 17 3782fg i out (a) 0 efficiency (%) 100 96 9894 92 90 88 86 7 3782 ta02b 12 4 6 3 5 8 12v in 15v in ef? ciency 10 cs2 c out2 330f, 35v, 2x + 27 2625 24 23 22 21 20 19 18 17 16 15 28 23 4 5 6 7 8 9 1011 12 13 14 1 10 cs1 59k 82k 274k 825k 2r2 24.9k 221k r c1 13.3k 10nf 4.7nf c c2 100pf c c1 6.8nf 2.2f c in 22f 25v c out1 22f, 25v, 4x 10nf 1f 3782 ta02 10v to 24v input q1ph3330 q2ph3330 output24v 8a l1, l2: pulse pb2020-103all ceramic capacitors are x7r, tdk *output current with both inputs present l1 pb2020-103 d1 ups840 l2 pb2020-103 d2 ups840 cs1 cs2 0.004 0.004 ? ? lt3782 v cc ncnc v ee1 bgate1 gbias1gbias2 bgate2 v ee2 nc run fb v c gbias sgate1nc gnd sync delay dcl sense1 + sense1 C sloper set sense2 C sense2 + ss sgate2 10v to 24v input to 24v, 8a output boost converter typical applications downloaded from: http:///
lt3782 18 3782fg fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation eb fe28 (eb) tssop 0204 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 134 5 6 7 8910 11 12 13 14 19 20 22 21 15 16 18 17 9.60 ? 9.80* (.378 ? .386) 4.75 (.187) 2.74 (.108) 28 2726 25 24 23 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.75 (.187) 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note:1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc package description downloaded from: http:///
lt3782 19 3782fg information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note:1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 0.10 27 28 12 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 package description downloaded from: http:///
lt3782 20 3782fg linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0109 rev g printed in usa related parts part number description comments lt ? 1619 current mode pwm controller 300khz fixed frequency, boost, sepic, flyback topology ltc1624 current mode dc/dc controller so-8; 300khz operating frequency; buck, boost, sepic design; v in up to 36v ltc1696 overvoltage protection controller 0.8v v in 24v, 2% overvoltage threshold accuracy, thinsot? package ltc1700 no r sense ? synchronous step-up controller up to 95% ef? ciency, operation as low as 0.9v input ltc1871/ltc1871-7 wide input range controller no r sense , 7v gate drive, current mode control lt1930 1.2mhz, sot-23 boost converter up to 34v output, 2.6v v in 16v, miniature design lt1952 single switch synchronous forward controller high ef? ciency, 25w to 500w, wide input range, adaptive duty cycle clamp ltc3425 5a, 8mhz 4-phase monolithic step-up dc/dc converter 0.5v v in 4.5v, 2.4v v out 5.25v, very low output ripple ltc3703/ltc3703-5 100v and 60v, step-down and step-up dc/dc synchronous controller high ef? ciency synchronous operation, high voltage operation, no transformer required ltc3728 dual, 550khz, 2-phase synchronous step-down controller dual 180 phased controllers, v in : 3.5v to 35v, 99% duty cycle, 5mm 5mm qfn, ssop-28 packages ltc3729 20a to 200a, 550khz polyphase? synchronous controller expandable from 2-phase to 12-phase, uses all surface mount components, v in up to 36v ltc3731 3- to 12-phase step-down synchronous controller 60a to 240a output current, 0.6v v out 6v, 4.5v v in 32v ltc3803 sot-23 flyback controller adjustable slope compensation, internal soft-start, current mode 200khz operation ltc3806 synchronous flyback controller high ef? ciency, improves cross regulation in multiple output designs, current mode, 3mm 4mm 12-pin dfn package 10 cs2 c out2 330f, 35v, 2x + bas516 27 2625 24 23 22 21 20 19 18 17 16 15 28 23 4 5 6 7 8 9 1011 12 13 14 1 10 cs1 59k 82k 274k 825k 2r2 24.9k 261k r c1 15k 10nf c ina 22f c inb 22f 4.7nf c c2 100pf c c1 4.7nf 2.2f c out1 10f, 50v, 4x 10nf bas516 1f 3782 ta03 v inb 0v to 28v* v ina 0v to 28v* q1ph4840s q2ph4840s output28v 4a (8a**) note:*input voltage range for vina and vinb is 0v to 28v. at least one of the inputs must be 12v or higher. l1, l2: pulse pb2020-103 all ceramic capacitors are x7r, tdk **output current with both inputs 12v or higher l1 10h d1 ups840 l2 10h d2 ups840 cs1 cs2 0.004 0.004 ? ? lt3782 v cc ncnc v ee1 bgate1 gbias1gbias2 bgate2 v ee2 nc run fb v c gbias sgate1nc gnd sync delay dcl sense1 + sense1 C sloper set sense2 C sense2 + ss sgate2 28v output base station power converter with redundant input polyphase is a registered trademark of linear technology corporation. thinsot and no r sense are trademarks of linear technology corporation. typical applications downloaded from: http:///

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